Presently a state-of-the art DRAM comprises a substrate with an array of memory cells, including transistors, that are arranged in rows and columns and connected by wordlines and bitlines and a peripheral device area with support circuitry, including transistors, for reading in and out binary digits (bits) stored in the memory cells. Typically, array transistors are all the same and are packed very densely in the array while peripheral transistors differ in size and are spaced further apart. Continued demand to shrink electronic devices has facilitated the design of DRAMs having greater density and smaller size. However, current manufacturing methods limit the size of the array and support circuitry components.
FIGS. 1 and 2 illustrate a prior art peripheral metal oxide semiconductor (MOS) transistor 1 in 0.14 μm groundrule. The MOS transistor is formed on a silicon substrate 3 and comprises a thin gate oxide layer 5 on the substrate. Typically, the gate oxide layer is silicon oxide and has a thickness of about 50 A. The MOS transistor further comprises a gate conductor 7, a gate cap insulator 9, two spacers 11, a dielectric layer 13, and a layer of silicon dioxide 15. Spaced apart and on either side of the gate conductor are periphery contact-to-diffusion (CD) openings or CD contacts 17, which form a source and a drain for the MOS transistor 1. The terms “drain” and “source” are used herein interchangeably to refer to the diffusion regions. The CD contacts are interconnected separately for the source and the drain by conductive metalization lines 19. In addition to the CD contacts, a contact-to-gate (CG) opening or CG contact 21 forms a contact to the gate conductor 7.
As shown in FIG. 2, the separation 23 between the CD contacts 17 and the gate conductor 7 is 0.14 μm, and the separation 25 between the metalization lines is 0.38 μm. The distance between the metalization lines, which includes the width of the gate conductor and the width of the CD contacts, determines the overall width of the transistor. The overall width 27 of the prior art MOS transistor in FIG. 2 is 0.94 μm.
During current manufacturing processes for DRAMs, the CD contacts 17 and the CG contacts 21 are patterned on the same photoresist mask, and then etched at the same time. A non-selective etching process is used to etch the CD and CG contacts because the contacts need to be etched through a thick layer of gate cap insulator 9 which is usually silicon nitride. The spacing between the gate conductor 7 and the CD contacts 17 must be at least 0.14 μm because a non-selective etch process is used. If the CD contacts 17 are closer than 0.14 μm to the gate conductor 7, the non-selective etching process may etch into the gate conductor if there is mask overlay shift and cause a short in the path. Because a minimum distance of 0.14 μm must be maintained, a limit is placed on the number of MOS transistors that will fit in a given area on a silicon wafer. Therefore, it would be advantageous to reduce the size or width of the MOS transistor in order to permit a higher number of MOS transistors to be placed on the periphery of the DRAM device.